(1) Field of the Invention
The present invention relates to a method for making integrated circuits on semiconductor substrates, and more particularly relates to a method for forming air-insulated multilevel wiring for interconnecting the discrete devices on integrated circuits.
(2) Description of the Prior Art
Integrated circuits fabricated on semiconductor substrates for Ultra-Large Scale Integration (ULSI) require multilevels of metal interconnections for electrically interconnecting the discrete semiconductor devices on the semiconductor chips. In the more conventional method the different levels of interconnections are separated by layers of insulating material. These interposed insulating layers have etched via holes which are used to connect one level of metal to the next. Typically, the insulating layer is a silicon oxide (SiO.sub.2) having a dielectric constant (relative to vacuum) of about 3.5 to 4.0. However, as the device dimensions decrease and the packing density increases, it is necessary to reduce the spacing between the metal lines in the interconnections to effectively wire-up the integrated circuits. Unfortunately, as the spacing decreases, the intra- and interlevel capacitances increase between metal lines when an insulating layer having the same dielectric constant is used since the capacitance is inversely proportional to the spacing between the lines. This, in turn, adversely affects the signal propagation time in the circuit since the response of the circuit is dependent on the RC delay time, where R is the resistance of the metal line, and C is the inter- and intralevel capacitance mentioned above.
One approach to minimize these time delays is to use an insulating material which has a lower dielectric coefficient, such as a polyimide. For example, polyimides can be used which have dielectric constant as low as 3.2 to 3.4.
Another method used to reduce the capacitance between the integrated circuit devices on silicon substrates and the substrate has been claimed by K. Beyer et al. in U.S. Pat. No. 5,306,659. In this method an N.sub.+ heavily doped buried epitaxy layer in the silicon substrate is selectively laterally etched underneath a lightly doped N.sub.- region which is then used as the device area. This reduces the capacitance between the semiconductor devices, such as field effect transistors (FETs) and bipolar transistors and the underlying semiconductor substrate.
There is still a need in the semiconductor industry for providing a simplified method for forming multilevel metal interconnections having reduced inter- and intralevel capacitance for reduced RC time delays and improved circuit performance.